Xavier/Ho_app
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Origin

Browse Source
This commit is contained in:
Xavier Walter
2025-12-06 18:21:19 +01:00
commit 603390c22e
31 changed files with 4299 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

146
Ho_Siren/Firmware/blink_pwm_baremetal/config/pin_config.h Normal file
View File

@@ -0,0 +1,146 @@
#ifndef PIN_CONFIG_H
#define PIN_CONFIG_H
// $[CMU]
// [CMU]$
// $[LFXO]
// [LFXO]$
// $[PRS.ASYNCH0]
// [PRS.ASYNCH0]$
// $[PRS.ASYNCH1]
// [PRS.ASYNCH1]$
// $[PRS.ASYNCH2]
// [PRS.ASYNCH2]$
// $[PRS.ASYNCH3]
// [PRS.ASYNCH3]$
// $[PRS.ASYNCH4]
// [PRS.ASYNCH4]$
// $[PRS.ASYNCH5]
// [PRS.ASYNCH5]$
// $[PRS.ASYNCH6]
// [PRS.ASYNCH6]$
// $[PRS.ASYNCH7]
// [PRS.ASYNCH7]$
// $[PRS.ASYNCH8]
// [PRS.ASYNCH8]$
// $[PRS.ASYNCH9]
// [PRS.ASYNCH9]$
// $[PRS.ASYNCH10]
// [PRS.ASYNCH10]$
// $[PRS.ASYNCH11]
// [PRS.ASYNCH11]$
// $[PRS.SYNCH0]
// [PRS.SYNCH0]$
// $[PRS.SYNCH1]
// [PRS.SYNCH1]$
// $[PRS.SYNCH2]
// [PRS.SYNCH2]$
// $[PRS.SYNCH3]
// [PRS.SYNCH3]$
// $[GPIO]
// [GPIO]$
// $[TIMER0]
// TIMER0 CC0 on PC03
#ifndef TIMER0_CC0_PORT
#define TIMER0_CC0_PORT SL_GPIO_PORT_C
#endif
#ifndef TIMER0_CC0_PIN
#define TIMER0_CC0_PIN 3
#endif
// [TIMER0]$
// $[TIMER1]
// [TIMER1]$
// $[TIMER2]
// [TIMER2]$
// $[TIMER3]
// [TIMER3]$
// $[USART0]
// [USART0]$
// $[USART1]
// [USART1]$
// $[USART2]
// [USART2]$
// $[I2C1]
// [I2C1]$
// $[LETIMER0]
// [LETIMER0]$
// $[IADC0]
// [IADC0]$
// $[ACMP0]
// [ACMP0]$
// $[ACMP1]
// [ACMP1]$
// $[I2C0]
// [I2C0]$
// $[PTI]
// [PTI]$
// $[MODEM]
// [MODEM]$
// $[CUSTOM_PIN_NAME]
#ifndef _PORT
#define _PORT SL_GPIO_PORT_A
#endif
#ifndef _PIN
#define _PIN 0
#endif
// [CUSTOM_PIN_NAME]$
#endif // PIN_CONFIG_H

284
Ho_Siren/Firmware/blink_pwm_baremetal/config/sl_clock_manager_oscillator_config.h Normal file
View File

@@ -0,0 +1,284 @@
/***************************************************************************//**
* @file
* @brief Clock Manager - Oscillators configuration file.
*******************************************************************************
* # License
* <b>Copyright 2025 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H
#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H
#if defined(SL_COMPONENT_CATALOG_PRESENT)
#include "sl_component_catalog.h"
#endif
// Internal Defines: DO NOT MODIFY
#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1
#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0
#if defined(SL_CATALOG_RAIL_LIB_PRESENT)
#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE
#else
#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE
#endif
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Oscillators Settings
// <h> HFXO Settings (if High Frequency crystal is used)
// <o SL_CLOCK_MANAGER_HFXO_EN> Enable
// <i> Enable to configure HFXO
// <i> AUTO enables HFXO if a radio is used
// <SL_CLOCK_MANAGER_HFXO_EN_AUTO=> AUTO
// <SL_CLOCK_MANAGER_HFXO_EN_ENABLE=> ENABLE
// <SL_CLOCK_MANAGER_HFXO_EN_DISABLE=> DISABLE
// <d> SL_CLOCK_MANAGER_HFXO_EN_AUTO
#ifndef SL_CLOCK_MANAGER_HFXO_EN
#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_ENABLE
#endif
// <o SL_CLOCK_MANAGER_HFXO_MODE> Mode
// <i>
// <HFXO_CFG_MODE_XTAL=> XTAL
// <HFXO_CFG_MODE_EXTCLK=> EXTCLK
// <d> HFXO_CFG_MODE_XTAL
#ifndef SL_CLOCK_MANAGER_HFXO_MODE
#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL
#endif
// <o SL_CLOCK_MANAGER_HFXO_FREQ> Frequency in Hz <38000000-40000000>
// <d> 38400000
#ifndef SL_CLOCK_MANAGER_HFXO_FREQ
#define SL_CLOCK_MANAGER_HFXO_FREQ 38400000
#endif
// <o SL_CLOCK_MANAGER_HFXO_CTUNE> CTUNE <0-255>
// <d> 140
#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE
#define SL_CLOCK_MANAGER_HFXO_CTUNE 140
#endif
// <o SL_CLOCK_MANAGER_HFXO_PRECISION> Precision in PPM <0-65535>
// <d> 50
#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION
#define SL_CLOCK_MANAGER_HFXO_PRECISION 50
#endif
// <q SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN> CTUNE HXFO manufacturing
// <i> Enable to use CTUNE HFXO manufacturing value for calibration
// <d> 1
#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN
#define SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN 1
#endif
// </h>
// <e> LFXO Settings (if Low Frequency crystal is used)
// <i> Enable to configure LFXO
#ifndef SL_CLOCK_MANAGER_LFXO_EN
#define SL_CLOCK_MANAGER_LFXO_EN 0
#endif
// <o SL_CLOCK_MANAGER_LFXO_MODE> Mode
// <i>
// <LFXO_CFG_MODE_XTAL=> XTAL
// <LFXO_CFG_MODE_BUFEXTCLK=> BUFEXTCLK
// <LFXO_CFG_MODE_DIGEXTCLK=> DIGEXTCLK
// <d> LFXO_CFG_MODE_XTAL
#ifndef SL_CLOCK_MANAGER_LFXO_MODE
#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL
#endif
// <o SL_CLOCK_MANAGER_LFXO_CTUNE> CTUNE <0-127>
// <d> 63
#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE
#define SL_CLOCK_MANAGER_LFXO_CTUNE 63
#endif
// <o SL_CLOCK_MANAGER_LFXO_PRECISION> LFXO precision in PPM <0-65535>
// <d> 50
#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION
#define SL_CLOCK_MANAGER_LFXO_PRECISION 50
#endif
// <o SL_CLOCK_MANAGER_LFXO_TIMEOUT> Startup Timeout Delay
// <i>
// <LFXO_CFG_TIMEOUT_CYCLES2=> CYCLES2
// <LFXO_CFG_TIMEOUT_CYCLES256=> CYCLES256
// <LFXO_CFG_TIMEOUT_CYCLES1K=> CYCLES1K
// <LFXO_CFG_TIMEOUT_CYCLES2K=> CYCLES2K
// <LFXO_CFG_TIMEOUT_CYCLES4K=> CYCLES4K
// <LFXO_CFG_TIMEOUT_CYCLES8K=> CYCLES8K
// <LFXO_CFG_TIMEOUT_CYCLES16K=> CYCLES16K
// <LFXO_CFG_TIMEOUT_CYCLES32K=> CYCLES32K
// <d> LFXO_CFG_TIMEOUT_CYCLES4K
#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT
#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K
#endif
// <q SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN> CTUNE LXFO manufacturing
// <i> Enable to use CTUNE LFXO manufacturing value for calibration
// <d> 1
#ifndef SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN
#define SL_CLOCK_MANAGER_CTUNE_MFG_LFXO_EN 1
#endif
// </e>
// <h> HFRCO and DPLL Settings
// <o SL_CLOCK_MANAGER_HFRCO_BAND> Frequency Band
// <i> RC Oscillator Frequency Band
// <cmuHFRCODPLLFreq_1M0Hz=> 1 MHz
// <cmuHFRCODPLLFreq_2M0Hz=> 2 MHz
// <cmuHFRCODPLLFreq_4M0Hz=> 4 MHz
// <cmuHFRCODPLLFreq_7M0Hz=> 7 MHz
// <cmuHFRCODPLLFreq_13M0Hz=> 13 MHz
// <cmuHFRCODPLLFreq_16M0Hz=> 16 MHz
// <cmuHFRCODPLLFreq_19M0Hz=> 19 MHz
// <cmuHFRCODPLLFreq_26M0Hz=> 26 MHz
// <cmuHFRCODPLLFreq_32M0Hz=> 32 MHz
// <cmuHFRCODPLLFreq_38M0Hz=> 38 MHz
// <cmuHFRCODPLLFreq_48M0Hz=> 48 MHz
// <cmuHFRCODPLLFreq_56M0Hz=> 56 MHz
// <cmuHFRCODPLLFreq_64M0Hz=> 64 MHz
// <cmuHFRCODPLLFreq_80M0Hz=> 80 MHz
// <d> cmuHFRCODPLLFreq_80M0Hz
#ifndef SL_CLOCK_MANAGER_HFRCO_BAND
#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz
#endif
// <e> Use DPLL
// <i> Enable to use the DPLL with HFRCO
#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN
#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0
#endif
// <o SL_CLOCK_MANAGER_DPLL_FREQ> Target Frequency in Hz <1000000-80000000>
// <i> DPLL target frequency
// <d> 80000000
#ifndef SL_CLOCK_MANAGER_DPLL_FREQ
#define SL_CLOCK_MANAGER_DPLL_FREQ 80000000
#endif
// <o SL_CLOCK_MANAGER_DPLL_N> Numerator (N) <300-4095>
// <i> Value of N for output frequency calculation fout = fref * (N+1) / (M+1)
// <d> 3999
#ifndef SL_CLOCK_MANAGER_DPLL_N
#define SL_CLOCK_MANAGER_DPLL_N 3999
#endif
// <o SL_CLOCK_MANAGER_DPLL_M> Denominator (M) <0-4095>
// <i> Value of M for output frequency calculation fout = fref * (N+1) / (M+1)
// <d> 1919
#ifndef SL_CLOCK_MANAGER_DPLL_M
#define SL_CLOCK_MANAGER_DPLL_M 1919
#endif
// <o SL_CLOCK_MANAGER_DPLL_REFCLK> Reference Clock
// <i> Reference clock source for DPLL
// <CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED=> DISABLED
// <CMU_DPLLREFCLKCTRL_CLKSEL_HFXO=> HFXO
// <CMU_DPLLREFCLKCTRL_CLKSEL_LFXO=> LFXO
// <CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0=> CLKIN0
// <d> CMU_DPLLREFCLKCTRL_CLKSEL_HFXO
#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK
#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO
#endif
// <o SL_CLOCK_MANAGER_DPLL_EDGE> Reference Clock Edge Detect
// <i> Edge detection for reference clock
// <cmuDPLLEdgeSel_Fall=> Falling Edge
// <cmuDPLLEdgeSel_Rise=> Rising Edge
// <d> cmuDPLLEdgeSel_Fall
#ifndef SL_CLOCK_MANAGER_DPLL_EDGE
#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall
#endif
// <o SL_CLOCK_MANAGER_DPLL_LOCKMODE> DPLL Lock Mode
// <i> Lock mode
// <cmuDPLLLockMode_Freq=> Frequency-Lock Loop
// <cmuDPLLLockMode_Phase=> Phase-Lock Loop
// <d> cmuDPLLLockMode_Freq
#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE
#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase
#endif
// <q SL_CLOCK_MANAGER_DPLL_AUTORECOVER> Automatic Lock Recovery
// <d> 1
#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER
#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1
#endif
// <q SL_CLOCK_MANAGER_DPLL_DITHER> Enable Dither
// <d> 0
#ifndef SL_CLOCK_MANAGER_DPLL_DITHER
#define SL_CLOCK_MANAGER_DPLL_DITHER 0
#endif
// </e>
// </h>
// <h> HFRCOEM23 Settings
// <o SL_CLOCK_MANAGER_HFRCOEM23_BAND> Frequency Band
// <i> RC Oscillator Frequency Band
// <cmuHFRCOEM23Freq_1M0Hz=> 1 MHz
// <cmuHFRCOEM23Freq_2M0Hz=> 2 MHz
// <cmuHFRCOEM23Freq_4M0Hz=> 4 MHz
// <cmuHFRCOEM23Freq_13M0Hz=> 13 MHz
// <cmuHFRCOEM23Freq_16M0Hz=> 16 MHz
// <cmuHFRCOEM23Freq_19M0Hz=> 19 MHz
// <cmuHFRCOEM23Freq_26M0Hz=> 26 MHz
// <cmuHFRCOEM23Freq_32M0Hz=> 32 MHz
// <cmuHFRCOEM23Freq_40M0Hz=> 40 MHz
// <d> cmuHFRCOEM23Freq_19M0Hz
#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND
#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz
#endif
// </h>
// <h> CLKIN0 Settings
// <o SL_CLOCK_MANAGER_CLKIN0_FREQ> Frequency in Hz <1000000-38000000>
// <d> 38000000
#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ
#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000
#endif
// </h>
// </h>
// <<< end of configuration section >>>
// <<< sl:start pin_tool >>>
// <cmu signal=CLKIN0 optional=true> SL_CLOCK_MANAGER_CLKIN0
// $[CMU_SL_CLOCK_MANAGER_CLKIN0]
// [CMU_SL_CLOCK_MANAGER_CLKIN0]$
// <<< sl:end pin_tool >>>
#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */

231
Ho_Siren/Firmware/blink_pwm_baremetal/config/sl_clock_manager_tree_config.h Normal file
View File

@@ -0,0 +1,231 @@
/***************************************************************************//**
* @file
* @brief Clock Manager - Clock Tree configuration file.
*******************************************************************************
* # License
* <b>Copyright 2025 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H
#define SL_CLOCK_MANAGER_TREE_CONFIG_H
#if defined(SL_COMPONENT_CATALOG_PRESENT)
#include "sl_component_catalog.h"
#endif
// Internal Defines: DO NOT MODIFY
// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE
// selection of each clock branch to the right HW register value.
#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF
#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE
#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD
#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC
#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB
#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA
#if defined(SL_CATALOG_RAIL_LIB_PRESENT)
#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO
#else
#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL
#endif
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Clock Tree Settings
// <o SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE> Default Clock Source Selection for HF clock branches
// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO=> AUTO
// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL=> HFRCODPLL
// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO=> HFXO
// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO=> FSRCO
// <i> Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value.
// <i> AUTO uses HFXO if a radio is used and HFRCODPLL otherwise
// <d> SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO
#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL
#endif
// <o SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE> Default Clock Source Selection for LF clock branches
// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO=> LFRCO
// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO=> LFXO
// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO=> ULFRCO
// <i> Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value.
// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO
#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO
#endif
// <h> System Clock Branch Settings
// <o SL_CLOCK_MANAGER_SYSCLK_SOURCE> Clock Source Selection for SYSCLK branch
// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE=> DEFAULT_HF
// <CMU_SYSCLKCTRL_CLKSEL_FSRCO=> FSRCO
// <CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL=> HFRCODPLL
// <CMU_SYSCLKCTRL_CLKSEL_HFXO=> HFXO
// <CMU_SYSCLKCTRL_CLKSEL_CLKIN0=> CLKIN0
// <i> Selection of the Clock source for SYSCLK
// <d> SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE
#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
#endif
// <o SL_CLOCK_MANAGER_HCLK_DIVIDER> HCLK branch divider
// <CMU_SYSCLKCTRL_HCLKPRESC_DIV1=> DIV1
// <CMU_SYSCLKCTRL_HCLKPRESC_DIV2=> DIV2
// <CMU_SYSCLKCTRL_HCLKPRESC_DIV4=> DIV4
// <i> HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface.
// <d> CMU_SYSCLKCTRL_HCLKPRESC_DIV1
#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER
#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1
#endif
// <o SL_CLOCK_MANAGER_PCLK_DIVIDER> PCLK branch divider
// <CMU_SYSCLKCTRL_PCLKPRESC_DIV1=> DIV1
// <CMU_SYSCLKCTRL_PCLKPRESC_DIV2=> DIV2
// <i> PCLK branch is derived from HCLK. This clock drives the APB bus interface.
// <d> CMU_SYSCLKCTRL_PCLKPRESC_DIV1
#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER
#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1
#endif
// </h>
// <h> Trace Clock Branches Settings
// <o SL_CLOCK_MANAGER_TRACECLK_SOURCE> Clock Source Selection for TRACECLK branch
// <CMU_TRACECLKCTRL_CLKSEL_HCLK=> HCLK
// <CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23=> HFRCOEM23
// <i> Selection of the Clock source for TRACECLK
// <d> CMU_TRACECLKCTRL_CLKSEL_HCLK
#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE
#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_HCLK
#endif
// </h>
// <h> High Frequency Clock Branches Settings
// <i> Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible
// <i> EM01GRPACLK clock the Timer peripherals
// <o SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE> Clock Source Selection for EM01GRPACLK branch
// <SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE=> DEFAULT_HF
// <CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL=> HFRCODPLL
// <CMU_EM01GRPACLKCTRL_CLKSEL_HFXO=> HFXO
// <CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23=> HFRCOEM23
// <CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO=> FSRCO
// <i> Selection of the Clock source for EM01GRPACLK
// <d> SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE
#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE
#endif
// <o SL_CLOCK_MANAGER_IADCCLK_SOURCE> Clock Source Selection for IADCCLK branch
// <CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK=> EM01GRPACLK
// <CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23=> HFRCOEM23
// <CMU_IADCCLKCTRL_CLKSEL_FSRCO=> FSRCO
// <i> Selection of the Clock source for IADCCLK
// <d> CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK
#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE
#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK
#endif
// </h>
// <h> Low Frequency Clock Branches Settings
// <o SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE> Clock Source Selection for EM23GRPACLK branch
// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE=> DEFAULT_LF
// <CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO=> LFRCO
// <CMU_EM23GRPACLKCTRL_CLKSEL_LFXO=> LFXO
// <CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO=> ULFRCO
// <i> Selection of the Clock source for EM23GRPACLK
// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE
#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#endif
// <o SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE> Clock Source Selection for EM4GRPACLK branch
// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE=> DEFAULT_LF
// <CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO=> LFRCO
// <CMU_EM4GRPACLKCTRL_CLKSEL_LFXO=> LFXO
// <CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO=> ULFRCO
// <i> Selection of the Clock source for EM4GRPACLK
// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE
#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#endif
// <o SL_CLOCK_MANAGER_RTCCCLK_SOURCE> Clock Source Selection for EM23GRPACLK branch
// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE=> DEFAULT_LF
// <CMU_RTCCCLKCTRL_CLKSEL_LFRCO=> LFRCO
// <CMU_RTCCCLKCTRL_CLKSEL_LFXO=> LFXO
// <CMU_RTCCCLKCTRL_CLKSEL_ULFRCO=> ULFRCO
// <i> Selection of the Clock source for RTCCCLK
// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#ifndef SL_CLOCK_MANAGER_RTCCCLK_SOURCE
#define SL_CLOCK_MANAGER_RTCCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#endif
// <o SL_CLOCK_MANAGER_WDOG0CLK_SOURCE> Clock Source Selection for WDOG0CLK branch
// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE=> DEFAULT_LF
// <CMU_WDOG0CLKCTRL_CLKSEL_LFRCO=> LFRCO
// <CMU_WDOG0CLKCTRL_CLKSEL_LFXO=> LFXO
// <CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO=> ULFRCO
// <CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024=> HCLKDIV1024
// <i> Selection of the Clock source for WDOG0CLK
// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE
#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#endif
// <o SL_CLOCK_MANAGER_WDOG1CLK_SOURCE> Clock Source Selection for WDOG1CLK branch
// <SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE=> DEFAULT_LF
// <CMU_WDOG1CLKCTRL_CLKSEL_LFRCO=> LFRCO
// <CMU_WDOG1CLKCTRL_CLKSEL_LFXO=> LFXO
// <CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO=> ULFRCO
// <CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024=> HCLKDIV1024
// <i> Selection of the Clock source for WDOG1CLK
// <d> SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE
#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE
#endif
// </h>
// <h> Mixed Frequency Clock Branch Settings
// <o SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE> Clock Source Selection for SYSTICKCLK branch
// <0=> HCLK
// <1=> EM23GRPACLK
// <i> Selection of the Clock source for SYSTICKCLK
// <d> 0
#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE
#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0
#endif
// </h>
// </h>
#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */
// <<< end of configuration section >>>

44
Ho_Siren/Firmware/blink_pwm_baremetal/config/sl_core_config.h Normal file
View File

@@ -0,0 +1,44 @@
/***************************************************************************//**
* @file
* @brief sl_core Configuration
*******************************************************************************
* # License
* <b>Copyright 2023 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
#ifndef SL_CORE_CONFIG_H
#define SL_CORE_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Core Abstraction Configuration
// <q SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING> Enables measurement of interrupt masking time for debugging purposes.
// <i> Default: 0
#define SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING 0
// </h>
// <<< end of configuration section >>>
#endif // SL_CORE_CONFIG_H

53
Ho_Siren/Firmware/blink_pwm_baremetal/config/sl_device_init_emu_config.h Normal file
View File

@@ -0,0 +1,53 @@
/***************************************************************************//**
* @file
* @brief DEVICE_INIT_EMU Config
*******************************************************************************
* # License
* <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
#ifndef SL_DEVICE_INIT_EMU_CONFIG_H
#define SL_DEVICE_INIT_EMU_CONFIG_H
#include "em_emu.h"
// <<< Use Configuration Wizard in Context Menu >>>
// <q> Allow debugger to remain connected in EM2
// <i> Force PD0B to stay on on EM2 entry. This allows the debugger to remain connected in EM2 and EM3.
// <i> Enabling debug connectivity results in an increased power consumption in EM2/EM3.
// <i> Default: 1
#define SL_DEVICE_INIT_EMU_EM2_DEBUG_ENABLE 1
// <o SL_DEVICE_INIT_EMU_EM4_PIN_RETENTION_MODE> EM4 pin retention mode
// <emuPinRetentionDisable=> No Retention: Pads enter reset state when entering EM4.
// <emuPinRetentionEm4Exit=> Retention through EM4: Pads enter reset state when exiting EM4.
// <emuPinRetentionLatch=> Retention through EM4 and wakeup.
// <i> Default: emuPinRetentionDisable
#define SL_DEVICE_INIT_EMU_EM4_PIN_RETENTION_MODE emuPinRetentionDisable
// <<< end of configuration section >>>
#endif // SL_DEVICE_INIT_EMU_CONFIG_H

51
Ho_Siren/Firmware/blink_pwm_baremetal/config/sl_memory_manager_region_config.h Normal file
View File

@@ -0,0 +1,51 @@
/***************************************************************************//**
* @file
* @brief Memory Heap and stack size configuration file.
*******************************************************************************
* # License
* <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef SL_MEMORY_MANAGER_REGION_CONFIG_H
#define SL_MEMORY_MANAGER_REGION_CONFIG_H
#include "sl_component_catalog.h"
// <h> Memory configuration
// <o SL_STACK_SIZE> Stack size for the application.
// <i> Default: 4096
// <i> The stack size configured here will be used by the stack that the
// <i> application uses when coming out of a reset.
#ifndef SL_STACK_SIZE
#define SL_STACK_SIZE 4096
#endif
// </h>
// <<< end of configuration section >>>
#endif /* SL_MEMORY_MANAGER_REGION_CONFIG_H */

84
Ho_Siren/Firmware/blink_pwm_baremetal/config/sl_pwm_init_led0_config.h Normal file
View File

@@ -0,0 +1,84 @@
/***************************************************************************//**
* @file
* @brief PWM Driver
*******************************************************************************
* # License
* <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
#ifndef SL_PWM_INIT_LED0_CONFIG_H
#define SL_PWM_INIT_LED0_CONFIG_H
#ifdef __cplusplus
extern "C" {
#endif
// <<< Use Configuration Wizard in Context Menu >>>
// <h>PWM configuration
// <o SL_PWM_LED0_FREQUENCY> PWM frequency [Hz]
// <i> Default: 10000
#define SL_PWM_LED0_FREQUENCY 10000
// <o SL_PWM_LED0_POLARITY> Polarity
// <PWM_ACTIVE_HIGH=> Active high
// <PWM_ACTIVE_LOW=> Active low
// <i> Default: PWM_ACTIVE_HIGH
#define SL_PWM_LED0_POLARITY PWM_ACTIVE_HIGH
// </h> end pwm configuration
// <<< end of configuration section >>>
// <<< sl:start pin_tool >>>
// <timer channel=OUTPUT> SL_PWM_LED0
// $[TIMER_SL_PWM_LED0]
#ifndef SL_PWM_LED0_PERIPHERAL
#define SL_PWM_LED0_PERIPHERAL TIMER0
#endif
#ifndef SL_PWM_LED0_PERIPHERAL_NO
#define SL_PWM_LED0_PERIPHERAL_NO 0
#endif
#ifndef SL_PWM_LED0_OUTPUT_CHANNEL
#define SL_PWM_LED0_OUTPUT_CHANNEL 0
#endif
// TIMER0 CC0 on PC03
#ifndef SL_PWM_LED0_OUTPUT_PORT
#define SL_PWM_LED0_OUTPUT_PORT SL_GPIO_PORT_C
#endif
#ifndef SL_PWM_LED0_OUTPUT_PIN
#define SL_PWM_LED0_OUTPUT_PIN 3
#endif
// [TIMER_SL_PWM_LED0]$
// <<< sl:end pin_tool >>>
#ifdef __cplusplus
}
#endif
#endif // SL_PWM_INIT_LED0_CONFIG_H

82
Ho_Siren/Firmware/blink_pwm_baremetal/config/sl_sleeptimer_config.h Normal file
View File

@@ -0,0 +1,82 @@
/***************************************************************************//**
* @file
* @brief Sleep Timer configuration file.
*******************************************************************************
* # License
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
*******************************************************************************
*
* SPDX-License-Identifier: Zlib
*
* The licensor of this software is Silicon Laboratories Inc.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*
******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef SL_SLEEPTIMER_CONFIG_H
#define SL_SLEEPTIMER_CONFIG_H
#define SL_SLEEPTIMER_PERIPHERAL_DEFAULT 0
#define SL_SLEEPTIMER_PERIPHERAL_RTCC 1
#define SL_SLEEPTIMER_PERIPHERAL_PRORTC 2
#define SL_SLEEPTIMER_PERIPHERAL_RTC 3
#define SL_SLEEPTIMER_PERIPHERAL_SYSRTC 4
#define SL_SLEEPTIMER_PERIPHERAL_BURTC 5
#define SL_SLEEPTIMER_PERIPHERAL_WTIMER 6
#define SL_SLEEPTIMER_PERIPHERAL_TIMER 7
// <o SL_SLEEPTIMER_PERIPHERAL> Timer Peripheral Used by Sleeptimer
// <SL_SLEEPTIMER_PERIPHERAL_DEFAULT=> Default (auto select)
// <SL_SLEEPTIMER_PERIPHERAL_RTCC=> RTCC
// <SL_SLEEPTIMER_PERIPHERAL_PRORTC=> Radio internal RTC (PRORTC)
// <SL_SLEEPTIMER_PERIPHERAL_RTC=> RTC
// <SL_SLEEPTIMER_PERIPHERAL_SYSRTC=> SYSRTC
// <SL_SLEEPTIMER_PERIPHERAL_BURTC=> Back-Up RTC (BURTC)
// <SL_SLEEPTIMER_PERIPHERAL_WTIMER=> WTIMER
// <SL_SLEEPTIMER_PERIPHERAL_TIMER=> TIMER
// <i> Selection of the Timer Peripheral Used by the Sleeptimer
#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_DEFAULT
// <o SL_SLEEPTIMER_TIMER_INSTANCE> TIMER/WTIMER Instance Used by Sleeptimer (not applicable for other peripherals)
// <i> Make sure TIMER instance size is 32bits. Check datasheet for 32bits TIMERs.
// <i> Default: 0
#define SL_SLEEPTIMER_TIMER_INSTANCE 0
// <q SL_SLEEPTIMER_WALLCLOCK_CONFIG> Enable wallclock functionality
// <i> Enable or disable wallclock functionalities (get_time, get_date, etc).
// <i> Default: 0
#define SL_SLEEPTIMER_WALLCLOCK_CONFIG 0
// <o SL_SLEEPTIMER_FREQ_DIVIDER> Timer frequency divider (not applicable for WTIMER/TIMER)
// <i> WTIMER/TIMER peripherals are always prescaled to 1024.
// <i> Default: 1
#define SL_SLEEPTIMER_FREQ_DIVIDER 1
// <q SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER> If Radio internal RTC (PRORTC) HAL is used, determines if it owns the IRQ handler. Enable, if no wireless stack is used.
// <i> Default: 0
#define SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER 0
// <q SL_SLEEPTIMER_DEBUGRUN> Enable DEBUGRUN functionality on hardware RTC.
// <i> Default: 0
#define SL_SLEEPTIMER_DEBUGRUN 0
#endif /* SLEEPTIMER_CONFIG_H */
// <<< end of configuration section >>>